Description
In this assignment, you are asked to complete the design of a RISC microprocessor called the DLX. The processor specifications are taken from the book Computer Architecture: A Quantitative Approach by David A. Patterson and John L. Hennessy. You are asked to design two of the pipeline blocks at the HDL level. These blocks would then be combined with the code for the rest of the chip (provided to you) and the entire design needs to be simulated, and debugged.
A block diagram of the DLX processor is shown here. The block diagram also traces out the flow through the pipeline of the different instructions. Do note that this figure shows the data and instruction memory as part of the design. The design you are given to start with does not include memory. These will be provided later in a test bench design into which you can plug in your design before you start simulation.
I. Brief description of DLX
DLX is a five-stage pipelined processor. The five stages are,
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Instruction fetch (IF)
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Instruction decode (ID)
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