Description
• Login/Logout System For An Online Game (Teamwork)
This part of the lab will be performed and submitted with your group partner. Only submit a single copy per group.
1.1 Problem De nition
In this part, you are going to implement a login/logout system for a simple online RPG (Role Playing Game) called Heroes of Logic in Verilog. The game consists of di erent characters with di ering at-tributes. In the game, there are two teams, namely, LogicPower and CengForce. You are expected to implement the login/logout system of this game which is summarized as follows:
Firstly, a user ID will be assigned for each player to be used to login/logout the game. Every user ID consists of a randomly produced 4-bit number. The most signi cant bit (MSB) of this 4-bit number represents the team and the remaining 3-bits represent the character. When a player wants to login the game by selecting a team from login menu, the system rst checks the MSB of the user ID, and decides whether the selected team and the team information represented by MSB of userID are same. If these are same, the system then checks whether the capacity of the determined team is not full and another player with the same ID did not login before: If all these conditions are satis ed, the user can login the game in this team. You are expected to design the system summarized above having the following speci cations:
1) Players can either login or logout the game in their teams with their user IDs.
2) The capacity of teams is ve.
3) Di erent players can have the same 4-bit code.
4) You should keep count of the current number of players logged in a team. In case a player login/l-ogouts from the game, the number of players for his/her team should be updated.
5) The login of players into the teams are arranged as follows:
a) If the MSB of user ID of a player is 0, the player can login the game only in LogicPower team.
b) If the MSB of user ID of a player is 1, the player can login the game only in CengForce team.
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6) If a player violates the rules described in item 5, the system will give a warning and the player will not be allowed to login.
7) In case a player wants to login the game in a team that is allowed, the following should be checked:
a) The system will check whether the player with the same 4-bit user ID exists in the team. If exists, the player is \not” allowed to login the game. (no warning is required)
b) The system will check whether the team is completely full or not. If the team is completely full, the player is not allowed to login the game and the system will give a warning.
8) Initially, number of logged in users in both teams will be 0.
9) If the number of logged in users in one or both of the teams are 0, the system will give warning(s).
10) If a player is allowed to login the game in a team, his/her user ID will be inserted into the memory of this team.
11) If a player wants to logout the game, his/her user ID will be deleted from the memory of his/her team.
12) There will be four modes in the system:
a) Login Mode:
i) Players can login the game only when the system is in Login Mode.
ii) If a player is allowed to login (correct team, no same user ID logged in before and enough capacity in the team), the system will record the user ID into the rst empty slot of the memory of that team. Otherwise, the player will not be allowed to login and the system will give a warning.
b) Logout Mode:
i) Only players who are currently logged in a team can logout the game with their user ID. It will not be tested that if a student who is not currently logged in the game can logout or not.
ii) If a player logouts the game, his/her 4-bit user ID recorded will be deleted from the memory of that team.
c) Find Mode: The user ID that is entered will be searched in the memory of the given team. If user ID is found, the system will give a warning.
d) List Mode:
i) It should be indicated if the system is in the list mode.
ii) In this mode, the user IDs that were stored in the given team’s memory will be displayed one by one in every pulse of the CLK. The order of the display is the order of the records in that memory.
iii) Empty slots should not be ignored while displaying the user IDs. The empty slots will be shown as \0000″.
13) Initially, each record of the team memories will be “0000”.
14) “0000” will not be used as user ID; hence, a player can not have \0000″ as his/her user ID.
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1.2 Input/Output Speci cations
userID represents 4-bit user ID.
Name
Type
Size
CLK is the clock input for the module.
userID
Input
4 bits
team is used for the selection of the team.
Clock (CLK)
Input
1 bit
team = 0 ) Team Logic Power
team
Input
1 bit
team = 1 ) Team Ceng Force
mode
Input
2 bits
mode indicates the selected mode among the following 4 modes:
numPlyLP
Output
8 bits
mode = 00 ) Logout mode
numPlyCF
Output
8 bits
mode = 01 ) Login mode
teamWng
Output
1 bit
mode = 10 ) Find mode
capWngLP
Output
1 bit
mode = 11 ) List mode
capWngCF
Output
1 bit
numPlyLP, numPlyCF keeps the number of current players
ndRes
Output
1 bit
already logged in Logic Power and Ceng Force teams, respectively.
teamWng shows whether the player wants to login to the correct or
listOut
Output
4 bits
listMode
Output
1 bit
wrong team.
teamW ng = 0 ) Correct team.
teamW ng = 1 ) Wrong team.
capWngLP/capWngCF shows whether Logic Power/Ceng Force
team is full/empty or not.
capW ngLP=capW ngCF = 1 ) Logic Power/Ceng Force team is
either full or empty.
capW ngLP=capW ngCF = 0 ) otherwise.
ndRes shows whether 4 bit user ID to be searched in the given team
memory is found or not.
findRes = 1 ) Found.
findRes = 0 ) Not found.
listOut shows the user ID in the given team’s memory sequentially
each time CLK pulse is given.
listMode indicates whether the system is in list mode or not.
listMode = 1 ) System is in list mode.
listMode = 0 ) Otherwise.
1.3 Sample Input/Output
Between current state and next state, there will be one CLK cycle.
Initial Values:
Team Logic Power Memory
0000 0000 0000 0000 0000
Team Ceng Force Memory
0000 0000 0000 0000 0000
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
1
1
0
No output
0
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a) A player with user ID 1000 wants to login the game in Ceng Force team and the system allows the login (correct team):
Current State
Team Logic Power Memory
0000 0000 0000 0000 0000
Team Ceng Force Memory
0000 0000 0000 0000 0000
userID
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
1000
1
01
0
1
1
0
No output
0
Next State
Team Logic Power Memory
0000 0000 0000 0000 0000
Team Ceng Force Memory
1000 0000 0000 0000 0000
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
1
0
0
No output
0
b) A player with user ID 1001 wants to login the game in Logic Power team and the system does not allow login (wrong team) and gives warning:
Current State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 1011 1100 1111
userID
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
1001
0
01
0
1
1
0
No output
0
Next State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 1011 1100 1111
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
1
1
1
0
No output
0
c) A player with user ID 0010 wants to login the game in Logic Power team and the system does not allow login since a player with same user ID is already logged in:
Current State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 1011 1100 0000
4
userID
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0010
0
01
0
1
0
0
No output
0
Next State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 1011 1100 0000
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
1
0
0
No output
0
d) A player with user ID 1001 logins the game in Ceng Force team and the capacity of Ceng Force memory gets full as a result and the system gives warning:
Current State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
userID
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
1001
1
01
0
1
0
0
No output
0
Next State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 1001 1100 1011
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
1
1
0
No output
0
e) A player with user ID 0100 logouts the game and the record is deleted from Logic Power Memory:
Current State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
userID
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0100
0
00
0
1
0
0
No output
0
Next State
Team Logic Power Memory
0001 0010 0000 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
5
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
0
0
0
No output
0
f) Listing the user IDs in Ceng Force memory in list mode:
Current State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
1
11
0
1
0
0
No output
0
Next State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
1
0
0
1000
1
In every CLK pulse, the listOut will display the next record. (1010, 0000, 1100, 1011). After all the records are displayed, it will start displaying from the beginning.
g) Searching the user ID 0100 in Logic Power memory:
Current State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
userID
team
mode
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0100
0
10
0
1
0
0
No output
0
Next State
Team Logic Power Memory
0001 0010 0100 0101 0110
Team Ceng Force Memory
1000 1010 0000 1100 1011
teamWng
capWngLP
capWngCF
ndRes
listOut
listMode
0
1
0
1
No output
0
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1.4 FPGA Implementation
You will be provided with a Board232.v le (and a ready-to-use Xilinx project), which will bind inputs and outputs of the FPGA board with your Verilog module. You are required to test your Verilog module on the FPGA boards.
Name
FPGA Board
Description
userID
SW7,SW6,SW5,SW4
Left-most 4 switches (A)
Clock (CLK)
BTN0
Right-most button (C)
team
SW0
Right-most switch (B)
mode
SW2,SW1
The next 2 switches next to SW0 (B)
teamWng
LD7
Left-most led (F)
capWngLP
LD0
Right-most led (G)
capWngCF
LD1
The led next to LD0 (G)
ndRes
LD2
The led next to LD1 (G)
listOut
7-segment display
(D) **
listMode
LD4
The led next to LD3 (E)
**:Each individual bit will be displayed in each component of the 7-segment display (D)
1.5 Deliverables
Implement your module in a single Verilog le: lab4 2.v. Do NOT submit your testbenches.You may share your testbenches on the newsgroup.
Submit the le through the COW system before the given deadline. April 25, 2018, 23:59hrs. This part is supposed to be done with your group partner. Make sure both of you take roles in
implementation of the project. Any kind of inter-group cheating is not allowed.
Use the newsgroup metu.ceng.course.232 for any questions regarding the homework.
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