Description
Corresponding TAs: Aditya Sasongko
Notes: You may discuss the problems with your peers but the submitted work must be your own work. No late assignment will be accepted. Submit a SOFT copy of your assignment to the blackboard *AND* submit a HARD copy of it to the COMP 303 mailboxes. This assignment is worth 4% of your total grade.
Problem 1
(10 pts)
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In MIPS assembly, write an assembly language version of the following C code segment. At the beginning of the segment, the only values in registers are the base address of arrays A and B in registers $a0 and $a1. To get credit, comment your code.
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int A[40], B[40];
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for (i=1; i < 40; i++) {
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B[i] = A[i] + A[i-1];
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A[i] = 5*B[i] ;
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}
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Compilers can optimize loops to reduce memory operations (loads and stores) for perfor-mance. Implement more optimized version of the above loop in assembly language that uses fewer memory instructions.
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COMP 303 – Computer Architecture ( Due: Oct 13, 2019, 6pm): HW1 PROBLEM 1
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//write your code for (a) here
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//write your code for (b) here
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Student Name: Page 2 of 7
COMP 303 – Computer Architecture ( Due: Oct 13, 2019, 6pm): HW1 PROBLEM 2
Problem 2
(6 pts) Suppose that you are asked to design a chip for an embedded system that will be used for gym equipment. Because of the cost and space restrictions, you decided to have 20-bit wide instructions and have only 16 general-purpose registers. Similar to MIPS, this chip uses a three-address ISA, which takes two sources, performs an operation on these sources and stores the result back into a destination register.
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How will your R-type instructions look like? Assume that there is no opcode extension and shift amount is represented in 3 bits.
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How many di erent instructions you can encode in this new ISA?
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How many bits should the immediate eld of an I-type instruction be to match the length on an R-type instruction?
Student Name: Page 3 of 7
COMP 303 – Computer Architecture ( Due: Oct 13, 2019, 6pm): HW1 PROBLEM 3
Problem 3
(20 pts ) 0-address machine uses a stack, where all operations are done using values stored on the stack. For example,
PUSH addr – pushes the value stored at memory location addr onto the stack. POP addr – pops the stack and stores the value into memory location addr
BOP addr – pops two values o the stack, performs the binary operation BOP on the two values, and pushes the result back onto the stack
For example, to compute A + B with 0-address machine, the following sequence of operations are necessary: PUSH A, PUSH B, ADD. After execution of ADD, A and B would no longer be on the stack, but the value A+B would be at the top of the stack.
Make the following assumptions for the next questions and the following code snippet.
The opcode size is 1 byte (8 bits).
All register operands are 1 byte (8 bits).
All memory addresses are 2 bytes (16 bits). All data values are 4 bytes (32 bits).
All instructions are an integral number of bytes in length.
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X=Y+Z;
Y=X+Z;
T=X-Y;
For (a), (b), (c), use the provided table. I-bytes refers to instruction bytes, D-bytes refers to data bytes.
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What is the assembly code for the above code for 0-address machine? Assume initially the variables X, Y, Z and T are in memory. Be sure to store the contents of variables back into memory. Do not modify any other values in memory.
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What is the assembly code for the above code for MIPS?
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Calculate the instruction bytes fetched and the memory-data bytes transferred (read or written) for 0-address machine and for MIPS.
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Which ISA is most e cient as measured by code size? Why?
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Which ISA is most e cient as measured by total memory tra c (code + data)? Why?
Student Name: Page 4 of 7
COMP 303 – Computer Architecture ( Due: Oct 13, 2019, 6pm): HW1 PROBLEM 3
Student Name: Page 5 of 7
COMP 303 – Computer Architecture ( Due: Oct 13, 2019, 6pm): HW1 PROBLEM 4
Problem 4
(10 pts) MIPS is just one of the Instruction Set Architectures and it is a simple one. Consider a more complex instruction set, called MAPS. One instruction in MAPS can perform the function of many instructions in MIPS. In this question, you are ask to implement the MIPS equivalent for a single instruction in MAPS, namely short int CP Y X, which is de ned as follows:
This instruction copies short integers from one address to another. The instruction uses three registers: CNT (count), SRC (source), and DST (destination). The CNT indicates the number of iterations. Each iteration, the instruction moves a short integer (two bytes data) from memory at address SRC to memory at address DST, and then increments both address pointers by two bytes. Thus, the instruction copies in total 2*CNT many bytes from source to destination.
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Write the corresponding MIPS code for short int CP Y X that performs the same func-tion. Assume $s1 = CNT; $s2 = SRC; $s3 = DST: Try to minimize code size as much as possible.
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b) Compare the code sizes of MIPS and MAPS for the same function in bytes. Which one is shorter?
Student Name: Page 6 of 7
COMP 303 – Computer Architecture ( Due: Oct 13, 2019, 6pm): HW1 PROBLEM 5
Problem 5
4 pts (This topic will be covered in the class soon)
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Instruction Type
Machine M1
Machine M2
Instruction
Cycles/Instruction
Cycles/Instruction
Frequency
Loads/Stores
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30%
ALU Operations
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60%
Branches
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10%
Consider two di erent implementations, Machine M1 and M2, of the same instruction set. There are three types of instructions (loads/stores, ALU operations and branches) in the instruction set. M1 has a clock rate of 800 MHz and M2 has a clock rate of 1.25 GHz. The average number of cycles for each instruction type and their frequencies for an image processing algorithm are provided in the table above.
a) Calculate the average CPI for each machine, M1 and M2.
b) Compare the CPU time of each machine for the image processing algorithm.
