Computer_Architecture:HW3 Solution

Description

Notes: This is an individual assignment (no groups). You may discuss the problems with your peers but the submitted work must be your own work. No late assignment will be accepted. Submit a SOFT copy of your assignment to the blackboard *AND* submit a HARD copy of it to the COMP 303 mailboxes or bring it to the class. This assignment is worth 4% of your total grade.

Problem 1

(25+25+10 pts) Consider a six-stage pipeline (IF, ID, EX, M1, M2, WB) processor where memory operations take two pipeline stages, so load result values are not available until after the M2 (memory) stage is completed. For this problem we will use the following assembly language sequence.

• myloop:

• ADD r1, r3, r1

• LW r1, 0(r1)

• SW r2, 0(r1)

4 SUBI r4, r4, 4

• LW r3, 0(r4)

• ADD r2, r2, r1

• BNEZ r4, myloop

• SUB r1, r3, r1

• OR r5, r1, r2

10. …

10. 1. Draw the pipeline timing diagram using the table below for the code sequence above.

Start with the rst instruction of the loop (line 1) and draw the timing diagram through one full loop iteration including the rst ADD of the second loop iteration.

Assume branches are resolved in the execution stage (EX) and branches are NOT taken. Show all stalls with an X and all the ushes with an F.

Show the forwardings with an arrow needed to help eliminate stalls and ll the forward-ing table with source and destination pipeline registers.

COMP 303 – Computer Architecture ( Due: Nov 13, 2019, 4:00 pm): HW3

PROBLEM 1

Cycles (time)

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

ADD

LW

SW

SUBI

LW

ADD

Bnez ….

Source Instruction	Source Location	Destination	Destination Location	Due to Register
(e.g. ADD r1, r3, r1)	(e.g. ID/EX)	Instruction	(e.g. ID/EX)	(e.g. R1)

COMP 303 – Computer Architecture ( Due: Nov 13, 2019, 4:00 pm): HW3 PROBLEM 1

2. Now assume that the architecture uses branch delay slots to try to eliminate all the branch penalty and compiler rearranges the code for the delay slots as follows:

• myloop:

• ADD r1, r3, r1

• LW r1, 0(r1)

• SW r2, 0(r1)

4 SUBI r4, r4, 4

• BNEZ r4, myloop

• LW r3, 0(r4)

• ADD r2, r2, r1

• SUB r1, r3, r1

• OR r5, r1, r2

10. …

Note that instructions 6 and 7 (lines 6 and 7) are \delay slot” instructions which means that they will be executed even when the branch in line 5 is taken. Draw the pipeline timing diagram and ll the forwarding table for this code. Start with the rst instruction of the loop (line 1) and draw the timing diagram through one full loop iteration including the rst ADD of the second loop iteration.

Cycles (time)

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

ADD

LW

SW

SUBI

Bnez

LW

ADD

…

COMP 303 – Computer Architecture ( Due: Nov 13, 2019, 4:00 pm): HW3 PROBLEM 1

Source Instruction	Source Location	Destination	Destination Location	Due to Register
(e.g. ADD r1, r3, r1)	(e.g. ID/EX)	Instruction	(e.g. ID/EX)	(e.g. R1)

3. Fill the table with RAW, WAW, and WAR dependencies for the above code example in

(b) where delay slot instructions are used.

	RAW			WAR			WAW
From	To	Due to	From	To	Due to	From	To	Due to
Instruc/on	Instruc/on	Register	Instruc/on	instruc/on	Register	Instruc/on	Instruc/on	Register
(Read)	(Write)		(Write)	(Read)		(Write)	(Write)