Description
21
You have to implement instruction and data memory and register modules. Use your 1-bit ALU in your previous design as a module.
You have to write your own testbench on Verilog and show that the project is working right.
Learn how to initialize and read a memory in PS.
Write a report that explains your Verilog modules and the testbench results. You should test all operations that ALU allows. Also report how many logic gates you used for the ALU.
RULES!!!
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Other than register and memory, you cannot use any other logic gates than AND, OR and NOT. (For instance XOR is not allowed.)
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You can only use structural Verilog. No dataflow, no assign statement no behavioral Verilog.
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ONLY THE INSTRUCTIONS IN THE TABLE WILL BE SUPPORTED. OTHERWISE 0pts.
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Any not simulating Verilog project gets at most 20pts.
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Any cheating means -100pts whether giving or taking the design.
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You have to use hierarchy and different modules as described here.
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The project will be explained in PS. So attend the PS.
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If you can show your design working on actual FPGA board than you get 20pts.