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CSE Project 3 R-type Single cycle MIPS with Structural Verilog Solution

$30.00 $24.00

You will design a MIPS processor but only supporting the R-type instructions in the MIPS Green Sheet. Only the register block in your design will be behavioral but other than that, all your design must be structural. Your MIPS will take a 32-bit instruction as input, so there will be no instruction memory. Also you…

5/5 – (2 votes)

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5/5 – (2 votes)

You will design a MIPS processor but only supporting the R-type instructions in the MIPS Green Sheet. Only the register block in your design will be behavioral but other than that, all your design must be structural.

Your MIPS will take a 32-bit instruction as input, so there will be no instruction memory. Also you will not implement lw/sw instructions therefore there will be no data memory.

The output of your block will be the output of ALU, but you also have to write the result to the $rd register as R-type instructions require.

Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, if-else, always, ?: and etc.

Use hierarchy in your project. For instance, you can design a Register module and use it as an instance in your datapath.

You will not support floating point instructions, I-type instructions or J-type instructions. Also you will not implement jr and slt. All other R-type instructions (including sltu) in the MIPS Green Sheet will be implemented.

You have to simulate all instructions by yourself via Modelsim and put the results in your report as well as to your zip folder including all your project files to submit to Moodle.

You can find MIPS Green Sheet at the last page.

You should write a report (20%) including:

  1. Your schematic designs for all modules.

  2. Your Verilog modules and their description.

  3. Modelsim Simulation results.

  1. If not compiling or partial working the explanation of which parts work which parts do not.

You will submit your report, your full project as a zip file to Moodle.

Rules:

  1. Behavioral or Dataflow Verilog are not allowed.

  1. Not compiling or not simulating solutions can at most get 25pts.

  2. You have to use Quartus II tool referred in Moodle.

  3. Each day of late submission will get 25 point loss.

  4. Write at least Register Block and Alu Control as modules.

  5. The name of your top module should be alu32.

  6. Do not change the previous ALU you designed. You must use it in your design without any modification inside.

Hint: Start with drawing schematic on paper for each module. Do not hesitate to write 32 lines of logic expressions for each bit of one or two 32-bit numbers whenever required.

Honor code: It is not a group project. Do not take any code from Internet. Any cheating means at least -100 for both sides. Do not share your codes and design to any one in any circumstance. Be honest and uncorrupt not to win but because it is RIGHT!

MIPS Reference Data Card (“Green Card”) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together

1

M I P SReference Data

CORE INSTRUCTION SET

OPCODE

FOR-

/ FUNCT

NAME, MNEMONIC

MAT

OPERATION (in Verilog)

(Hex)

Add

add

R

R[rd] = R[rs] + R[rt]

(1)

0 / 20hex

Add Immediate

addi

I

R[rt] = R[rs] + SignExtImm

(1,2)

8hex

Add Imm. Unsigned

addiu

I

R[rt] = R[rs] + SignExtImm

(2)

9hex

Add Unsigned

addu

R

R[rd] = R[rs] + R[rt]

0 / 21hex

And

and

R

R[rd] = R[rs] & R[rt]

0 / 24hex

And Immediate

andi

I

R[rt] = R[rs] & ZeroExtImm

(3)

chex

Branch On Equal

beq

I

if(R[rs]==R[rt])

4hex

PC=PC+4+BranchAddr

(4)

Branch On Not Equal bne

I

if(R[rs]!=R[rt])

5hex

PC=PC+4+BranchAddr

(4)

Jump

j

J

PC=JumpAddr

(5)

2hex

Jump And Link

jal

J

R[31]=PC+8;PC=JumpAddr

(5)

3hex

Jump Register

jr

R

PC=R[rs]

0 / 08hex

Load Byte Unsigned

lbu

I

R[rt]={24’b0,M[R[rs]

24hex

+SignExtImm](7:0)}

(2)

Load Halfword

lhu

I

R[rt]={16’b0,M[R[rs]

25hex

Unsigned

+SignExtImm](15:0)}

(2)

Load Linked

ll

I

R[rt] = M[R[rs]+SignExtImm]

(2,7)

30hex

Load Upper Imm.

lui

I

R[rt] = {imm, 16’b0}

fhex

Load Word

lw

I

R[rt] = M[R[rs]+SignExtImm]

(2)

23hex

Nor

nor

R

R[rd] = ~ (R[rs] | R[rt])

0 / 27hex

Or

or

R

R[rd] = R[rs] | R[rt]

0 / 25hex

Or Immediate

ori

I

R[rt] = R[rs] | ZeroExtImm

(3)

dhex

Set Less Than

slt

R

R[rd] = (R[rs] < R[rt]) ? 1 : 0

0 / 2ahex

Set Less Than Imm.

slti

I

R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2)

ahex

Set Less Than Imm.

sltiu

I

R[rt] = (R[rs] < SignExtImm)

bhex

Unsigned

?1:0

(2,6)

Set Less Than Unsig. sltu

R

R[rd] = (R[rs] < R[rt]) ? 1 : 0

(6)

0 / 2bhex

Shift Left Logical

sll

R

R[rd] = R[rt] << shamt

0 / 00hex

Shift Right Logical

srl

R

R[rd] = R[rt] >> shamt

0 / 02hex

Store Byte

sb

I

M[R[rs]+SignExtImm](7:0) =

28hex

R[rt](7:0)

(2)

Store Conditional

sc

I

M[R[rs]+SignExtImm] = R[rt];

38hex

R[rt] = (atomic) ? 1 : 0

(2,7)

Store Halfword

sh

I

M[R[rs]+SignExtImm](15:0) =

29hex

R[rt](15:0)

(2)

Store Word

sw

I

M[R[rs]+SignExtImm] = R[rt]

(2)

2bhex

Subtract

sub

R

R[rd] = R[rs] – R[rt]

(1)

0 / 22hex

Subtract Unsigned

subu

R

R[rd] = R[rs] – R[rt]

0 / 23hex

  1. May cause overflow exception

  2. SignExtImm = { 16{immediate[15]}, immediate }

  3. ZeroExtImm = { 16{1b’0}, immediate }

  4. BranchAddr = { 14{immediate[15]}, immediate, 2’b0 }

  5. JumpAddr = { PC+4[31:28], address, 2’b0 }

  6. Operands considered unsigned numbers (vs. 2’s comp.)

  1. Atomic test&set pair; R[rt] = 1 if pair atomic, 0 if not atomic

BASIC INSTRUCTION FORMATS

R

opcode

rs

rt

rd

shamt

funct

31

26 25

21 20

16 15

11 10

6 5

0

I

opcode

rs

rt

immediate

31

26 25

21 20

16 15

0

J

opcode

address

31

26 25

0

ARITHMETIC CORE INSTRUCTION SET

2

OPCODE

/ FMT /FT

FOR-

/ FUNCT

NAME, MNEMONIC

MAT

OPERATION

(Hex)

Branch On FP True

bc1t

FI

if(FPcond)PC=PC+4+BranchAddr (4)

11/8/1/–

Branch On FP False bc1f

FI

if(!FPcond)PC=PC+4+BranchAddr(4)

11/8/0/–

Divide

div

R

Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt]

0/–/–/1a

Divide Unsigned

divu

R

Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt]

(6) 0/–/–/1b

FP Add Single

add.s

FR

F[fd ]= F[fs] + F[ft]

11/10/–/0

FP Add

add.d

FR

{F[fd],F[fd+1]} = {F[fs],F[fs+1]} +

11/11/–/0

Double

{F[ft],F[ft+1]}

FP Compare Single

c.x.s*

FR

FPcond = (F[fs] op F[ft]) ? 1 : 0

11/10/–/y

FP Compare

c.x.d*

FR

FPcond = ({F[fs],F[fs+1]} op

11/11/–/y

Double

{F[ft],F[ft+1]}) ? 1 : 0

* (x is eq, lt, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e)

FP Divide Single

div.s

FR

F[fd] = F[fs] / F[ft]

11/10/–/3

FP Divide

div.d

FR

{F[fd],F[fd+1]} = {F[fs],F[fs+1]} /

11/11/–/3

Double

{F[ft],F[ft+1]}

FP Multiply Single

mul.s

FR

F[fd] = F[fs] * F[ft]

11/10/–/2

FP Multiply

mul.d

FR

{F[fd],F[fd+1]} = {F[fs],F[fs+1]} *

11/11/–/2

Double

{F[ft],F[ft+1]}

FP Subtract Single

sub.s

FR

F[fd]=F[fs] – F[ft]

11/10/–/1

FP Subtract

sub.d

FR

{F[fd],F[fd+1]} = {F[fs],F[fs+1]} –

11/11/–/1

Double

{F[ft],F[ft+1]}

Load FP Single

lwc1

I

F[rt]=M[R[rs]+SignExtImm]

(2) 31/–/–/–

Load FP

ldc1

I

F[rt]=M[R[rs]+SignExtImm];

(2)

35/–/–/–

Double

F[rt+1]=M[R[rs]+SignExtImm+4]

Move From Hi

mfhi

R

R[rd] = Hi

0 /–/–/10

Move From Lo

mflo

R

R[rd] = Lo

0 /–/–/12

Move From Control mfc0

R

R[rd] = CR[rs]

10 /0/–/0

Multiply

mult

R

{Hi,Lo} = R[rs] *

R[rt]

0/–/–/18

Multiply Unsigned

multu

R

{Hi,Lo} = R[rs] *

R[rt]

(6) 0/–/–/19

Shift Right Arith.

sra

R

R[rd] = R[rt] >>> shamt

0/–/–/3

Store FP Single

swc1

I

M[R[rs]+SignExtImm] = F[rt]

(2) 39/–/–/–

Store FP

sdc1

I

M[R[rs]+SignExtImm] = F[rt];

(2)

3d/–/–/–

Double

M[R[rs]+SignExtImm+4] = F[rt+1]

FLOATING-POINT INSTRUCTION FORMATS

FR

opcode

fmt

ft

fs

fd

funct

31

26 25

21 20

16 15

11 10

6 5

0

FI

opcode

fmt

ft

immediate

31

26 25

21 20

16 15

0

PSEUDOINSTRUCTION SET

NAME

MNEMONIC

OPERATION

Branch Less Than

blt

if(R[rs]<R[rt]) PC = Label

Branch Greater Than

bgt

if(R[rs]>R[rt]) PC = Label

Branch Less Than or Equal

ble

if(R[rs]<=R[rt]) PC = Label

Branch Greater Than or Equal

bge

if(R[rs]>=R[rt]) PC = Label

Load Immediate

li

R[rd] = immediate

Move

move

R[rd] = R[rs]

REGISTER NAME, NUMBER, USE, CALL CONVENTION

NAME NUMBER

USE

PRESERVEDACROSS

A CALL?

$zero

0

The Constant Value 0

N.A.

$at

1

Assembler Temporary

No

$v0-$v1

2-3

Values for Function Results

No

and Expression Evaluation

$a0-$a3

4-7

Arguments

No

$t0-$t7

8-15

Temporaries

No

$s0-$s7

16-23

Saved Temporaries

Yes

$t8-$t9

24-25

Temporaries

No

$k0-$k1

26-27

Reserved for OS Kernel

No

$gp

28

Global Pointer

Yes

$sp

29

Stack Pointer

Yes

$fp

30

Frame Pointer

Yes

$ra

31

Return Address

No

Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed.

CSE Project 3 R-type Single cycle MIPS with Structural Verilog Solution
$30.00 $24.00
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