Description
Problem 1 (25 points):
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EECS 485 |
HW1 |
Due: Sept 14 |
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Problem 4 (25 points): This problem relates to the design of equality |
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functions in CMOS. The function takes two n input variables A and B |
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and produces an output Z as shown in P4.a. |
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A solution to the realization of the equality function for two n input |
P4.a |
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variables would be to repeat a single variable cell N times. |
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Appropriate information is transmitted between cells as shown in the |
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figure P4.b. Design a cell in static CMOS at the transistor level which, |
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when repeated as above, implements the equality function. |
P4.b |
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Problem 5(15 points): Minimize the given Boolean equations to |
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eliminate redundancy (a’ means the complement of a) |
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1) ab + bdc + ca’ |
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2) (x+y)(x+z) |
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3) a(b+c+d) + b(c+d+a) + c(d+a+b) + d(a+b+c) |
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Problem 6 (25 points): Label the inputs of the circuit P6 so that it
implements the function: d (b + b’ c) + a b c’ + a’ b c
P6
Problem 7(15points): This problem relates to the design of circuits
using multiplexer modules. Three 2-to1 multiplexer modules can be combined to produce a 4-to-1 multiplexer. Any 2-input logic function can be implemented using this 4-to-1 multiplexer with the two inputs fed to the select line and the truth table entries appropriately fed to the input lines. However, a 4-to-1 multiplexer can also implement a 3-input logic function if the complement of one of the inputs is also available. Can you figure this out? You are to implement the logic function F(a,b,c)= ∑(0,2,7) using three of the 2-to-1 multiplexer modules.
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Design a gate-level implementation of the above function using multiplexer modules made of NAND/NOR gates.
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How many transistors are needed for the gate level implementation?
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If the same function is implemented using multiplexers with transmission gates, what would be the number of transistors needed for this implementation?
Problem 7(15): Draw the transistor schematic representing the circuit below. Can you describe the function of the circuit?
