Systems and Networks Project 1 Solution

Description

• Requirements

Download the proper version of CircuitSim. A copy of CircuitSim is available under Files on Canvas. You may also download it from the CircuitSim website (https://ra4king.github.io/CircuitSim/). In order to run CircuitSim, Java must be installed. If you are a Mac user, you may need to right-click on the JAR le and select \Open” in the menu to bypass Gatekeeper restrictions.

CircuitSim is still under development and may have unknown bugs. Please back up your work using some form of version control, such as a local/private git repository or Dropbox. Do not use public git repositories; it is against the Georgia Tech Honor Code.

The RAMA-2200 assembler is written in Python. If you do not have Python 2.6 or newer installed on your system, you will need to install it before you continue.

• Project Overview and Description

Project 1 is designed to give you a good feel for exactly how a processor works. In Phase 1, you will design a datapath in CircuitSim to implement a supplied instruction set architecture. You will use the datapath as a tool to determine the control signals needed to execute each instruction. In Phases 2 and 3, you are required to build a simple nite state machine (the \control unit”) to control your computer and actually run programs on it.

Note: You will need to have a working knowledge of CircuitSim. Make sure that you know how to make basic circuits as well as subcircuits before proceeding. The TAs are always here if you need help.

Project 1 CS2200 – Systems and Networks Fall 2019

• Phase 1 – Implement the Datapath

RAMA-2200 Datapath

Project 1 CS2200 – Systems and Networks Fall 2019

3.1.2 Debugging

As you build the datapath, you should consider adding functionality that will allow you to operate the whole datapath by hand. This will make testing individual operations quite simple. We suggest your datapath include devices that will allow you to put arbitrary values on the bus and to view the current value of the bus. Feel free to add any additional hardware that will help you understand what is going on.

3.1.3 Memory Addresses

Because of CircuitSim limitations, the RAM module is limited to no more than 16 address bits. Therefore, per our ISA, any 32-bit values used as memory addresses will be truncated to 16 bits (with the 16 most signi cant bits disregarded). We recommend you implement this (i.e. truncate the most signi cant bits) before feeding the address value from the MAR (Memory Address Register) to the RAM.

3.1.4 Comparison Logic

The \comparison logic” box in Figure 1 is responsible for performing the comparison logic associated with the SKP instruction. The comparison logic should read the current value on the bus plus the mode bits from the IR. When executing SKP, you should compute A B using the ALU. While this result of the ALU is being driven on the bus, the comparison logic should read the result A B and output a single \true” or \false” bit for either the condition A == B or A < B depending on the mode input.

Your comparison logic should be purely combinational. Feel free to use any CircuitSim components you wish to aid in your implementation.

3.1.5 Register File

You must implement your own register le. That is to say, you cannot use CircuitSim’s built-in RAM to create the register le. Consider what logic components you may want to use to implement addressing functionality (multiplexers, demultiplexers, decoders, etc). Your zero register must be implemented such that writes to it are ine ective, i.e., attempting to write a non-zero value to the zero register will do nothing. Do not forget to do this or you will lose points!

3.1.6 Register Select

From lecture and the textbook, you should be familiar with the \register select” (RegSel) multiplexer. The mux is responsible for feeding the register number from the correct eld in the instruction into the register le. See Table 4 for a list of inputs your mux should have.

• Phase 2 – Implement the Microcontrol Unit

In this phase of the project, you will use CircuitSim to implement the microcontrol unit for the RAMA-2200 processor. This component is referred to as the \Control Logic” in the images and schematics. The microcontroller will contain all of the signal lines to the various parts of the datapath.

You must do the following:

1. Read and understand the microcontroller logic:

Please refer to Appendix B: Microcontrol Unit for details.

Project 1 CS2200 – Systems and Networks Fall 2019

Note: You will be required to generate the control signals for each state of the processor in the next phase, so make sure you understand the connections between the datapath and the microcontrol unit before moving on.

2. Implement the Microcontrol Unit using CircuitSim. The appendix contains all of the necessary in-formation. Take note that the input and output signals on the schematics directly match the signals marked in the RAMA-2200 datapath schematic (see Figure 1).

• Phase 3 – Microcode and Testing

In this nal stage of the project, you will write the microcode control program that will be loaded into the microcontrol unit you implemented in Phase 2. Then, you will hook up the control unit you built in Phase 2 of the project to the datapath you implemented in Phase 1. Finally, you will test your completed computer using a simple test program and ensure that it properly executes.

In order to generate the microcode, we have provided you a program called MCGen. This program is specially designed to read and write .mc les, and output .dat les that can be read by CircuitSim. Do not modify the le called con g.txt; this le contains the microcode speci cation. Note: MCGen was created recently and is being used for the rst time this semester. Not all bugs are known, so save frequently and consider backing up your les. If you nd a bug, feel free to let the TAs know on Piazza.

You must do the following:

1. Open and ll out microcode.mc using MCGen. You will need to mark which control signal is high (that is 1) for each of the states.

2. Export your ROMs (Main ROM, Sequencer ROM, and Condition ROM) to .dat les. You will not turn in any of these les, they are just intermediate les that can be read by CircuitSim.

3. Import the ROMs in CircuitSim using the “Load from le” option in the ROM’s “Edit contents” menu.

4. Connect the completed control unit to the datapath you implemented in Phase 1. Using Figures 1 and 2, connect the control signals to their appropriate spots.

5. Finally, it is time to test your completed computer. Use the provided assembler (found in the \as-sembly” folder) to convert a test program from assembly to hex. For instructions on how to use the assembler and simulator, see README.txt in the \assembly” folder. Note: The simulator does not test your project, it simply provides a model. To test your design, you must load the assembled HEX into CircuitSim. We recommend using test programs that contain a single instruction since you are bound to have a few bugs at this stage of the project. Once you have built con dence, test your processor with the provided pow.s program as a more comprehensive test case.

• Deliverables

Please submit all of the following les in a .tar.gz archive generated by one of the following:

On Linux/Mac: Use the provided Make le. The Make le will work on any Unix or Linux-based machine (on Ubuntu, you may need to sudo apt-get install build-essential if you have never installed the build tools). Run make submit to automatically package your project into the correct archive format.

On Windows: Use the provided submit.bat script. Submitting through this method will require 7zip (https://www.7-zip.org/) to be installed on your system. Run submit.bat to automatically package your project into the correct archive format.

The generated archive should contain at a minimum the following les:

Project 1 CS2200 – Systems and Networks Fall 2019

CircuitSim datapath le (RAMA-2200.sim) Microcode le (microcode.mc)

Always re-download your assignment from Canvas after submitting to ensure that all necessary les were properly uploaded. If what we download does not work, you will get a 0 regardless of what is on your machine.

This project will be demoed. In order to receive full credit, you must sign up for a demo slot and complete the demo. We will announce when demo times are released.

Project 1 CS2200 – Systems and Networks Fall 2019

• Appendix A: RAMA-2200 Instruction Set Architecture

The RAMA-2200 is a simple, yet capable computer architecture. The RAMA-2200 combines attributes of both ARM and the LC-2200 ISA de ned in the Ramachandran & Leahy textbook for CS 2200.

The RAMA-2200 is a word-addressable, 32-bit computer. All addresses refer to words, i.e. the rst word (four bytes) in memory occupies address 0x0, the second word, 0x1, etc.

All memory addresses are truncated to 16 bits on access, discarding the 16 most signi cant bits if the address was stored in a 32-bit register. This provides roughly 64 KB of addressable memory.

7.1 Registers

The RAMA-2200 has 16 general-purpose registers. While there are no hardware-enforced restraints on the uses of these registers, your code is expected to follow the conventions outlined below.

Table 1: Registers and their Uses

Register Number	Name	Use	Callee Save?
0	$zero	Always Zero	NA
1	$at	Assembler/Target Address	NA
2	$v0	Return Value	No
3	$a0	Argument 1	No
4	$a1	Argument 2	No
5	$a2	Argument 3	No
6	$t0	Temporary Variable	No
7	$t1	Temporary Variable	No
8	$t2	Temporary Variable	No
9	$s0	Saved Register	Yes
10	$s1	Saved Register	Yes
11	$s2	Saved Register	Yes
12	$k0	Reserved for OS and Traps	NA
13	$sp	Stack Pointer	No
14	$fp	Frame Pointer	Yes
15	$ra	Return Address	No

1. Register 0 is always read as zero. Any values written to it are discarded. Note: for the purposes of this project, you must implement the zero register. Regardless of what is written to this register, it should always output zero.

2. Register 1 is used to hold the target address of a jump. It may also be used by pseudo-instructions generated by the assembler.

3. Register 2 is where you should store any returned value from a subroutine call.

4. Registers 3 – 5 are used to store function/subroutine arguments. Note: registers 2 through 8 should be placed on the stack if the caller wants to retain those values. These registers are fair game for the callee (subroutine) to trash.

5. Registers 6 – 8 are designated for temporary variables. The caller must save these registers if they want these values to be retained.

6. Registers 9 – 11 are saved registers. The caller may assume that these registers are never tampered with by the subroutine. If the subroutine needs these registers, then it should place them on the stack and restore them before they jump back to the caller.

Project 1 CS2200 – Systems and Networks Fall 2019

7. Register 12 is reserved for handling interrupts. While it should be implemented, it otherwise will not have any special use on this assignment.

7. Register 13 is your anchor on the stack. It keeps track of the top of the activation record for a subroutine.

7. Register 14 is used to point to the rst address on the activation record for the currently executing process.

7. Register 15 is used to store the address a subroutine should return to when it is nished executing.

7.2 Instruction Overview

The RAMA-2200 supports a variety of instruction forms, only a few of which we will use for this project.

The instructions we will implement in this project are summarized below.

Table 2: RAMA-2200 Instruction Set

31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

ADD	0000	DR	SR1	unused	SR2
NAND
	0001	DR	SR1	unused	SR2
ADDI
	0010	DR	SR1	immval20
LW
	0011	DR	BaseR	o set20
SW
	0100	SR	BaseR	o set20
GOTO
	0101	0000	unused	PCo set20
JALR
	0110	RA	AT	unused
HALT
	0111			unused
SKP
	1000	mode	SR1	unused	SR2
LEA
	1001	DR	unused	PCo set20

7.2.1 Conditional Branching

Conditional branching in the RAMA-2200 ISA is provided via two instructions: the SKP (\skip”) instruction and the GOTO (\unconditional branch”) instruction. The SKP instruction compares two registers and skips the immediately following instruction if the comparison evaluates to true. If the action to be conditionally executed is only a single instruction, it can be placed immediately following the SKP instruction. Otherwise a GOTO can be placed following the SKP instruction to branch over to a longer sequence of instructions to be conditionally executed.

Project 1 CS2200 – Systems and Networks Fall 2019

7.3 Detailed Instruction Reference

7.3.1 ADD

Assembler Syntax

ADD DR, SR1, SR2

Encoding

31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Project 1 CS2200 – Systems and Networks Fall 2019

7.3.3 ADDI

Assembler Syntax

ADDI DR, SR1, immval20

Encoding

31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Project 1 CS2200 – Systems and Networks Fall 2019

7.3.5 SW

Assembler Syntax

SW SR, offset20(BaseR)

Encoding

31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Project 1 CS2200 – Systems and Networks Fall 2019

7.3.7 JALR

Assembler Syntax

JALR RA, AT

Encoding

31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Project 1 CS2200 – Systems and Networks Fall 2019

7.3.9 SKP

Assembler Syntax

SKPE SR1, SR2

SKPLT SR1, SR2

Encoding

31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Project 1 CS2200 – Systems and Networks Fall 2019

• Appendix B: Microcontrol Unit

You will make a microcontrol unit which will drive all of the control signals to various items on the datapath. This Finite State Machine (FSM) can be constructed in a variety of ways. You could implement it with combinational logic and ip ops, or you could hard-wire signals using a single ROM. The single ROM solution will waste a tremendous amount of space since most of the microstates do not depend on the opcode or the conditional test to determine which signals to assert. For example, since the condition line is an input for the address, every microstate would have to have an address for condition = 0 as well as condition = 1, even though this only matters for one particular microstate.

To solve this problem, we will use a three ROM microcontroller. In this arrangement, we will have three

ROMs:

the main ROM, which outputs the control signals,

the sequencer ROM, which helps to determine which microstate to go at the end of the FETCH state, and the condition ROM, which helps determine whether or not to skip during the SKP instruction.

Examine the following:

Figure 2: Three ROM Microcontrol Unit

As you can see, there are three di erent locations that the next state can come from: part of the output from the previous state (main ROM), the sequencer ROM, and the condition ROM. The mux controls which of these sources gets through to the state register. If the previous state’s \next state” eld determines where to go, neither the OPTest nor ChkCmp signals will be asserted. If the opcode from the IR determines the next state (such as at the end of the FETCH state), the OPTest signal will be asserted. If the comparison circuitry determines the next state (such as in the SKP instruction), the ChkCmp signal will be asserted. Note that these two signals should never be asserted at the same time since nothing is input into the \11″ pin on the MUX.

Project 1 CS2200 – Systems and Networks Fall 2019

The sequencer ROM should have one address per instruction, and the condition ROM should have one address for condition true and one for condition false.

Before getting down to speci cs you need to determine the control scheme for the datapath. To do this examine each instruction, one by one, and construct a nite state bubble diagram showing exactly what control signals will be set in each state. Also determine what are the conditions necessary to pass from one state to the next. You can experiment by manually controlling your control signals on the bus you’ve created in Phase 1 – Implement the Datapath to make sure that your logic is sound.

Once the nite state bubble diagram is produced, the next step is to encode the contents of the Control Unit ROM using MCGen. Then you must design and build (in CircuitSim) the Control Unit circuit which will contain the three ROMs, a MUX, and a state register. Your design will be better if it allows you to single step and ensure that it is working properly. Finally, you will load the Control Unit’s ROMs with the hexadecimal generated by MCGen’s export feature.

Note that the input address to the ROM uses bit 0 for the lowest bit of the current state and 5 for the highest bit for the current state.

Table 3: ROM Output Signals

Bit	Purpose	Bit	Purpose	Bit	Purpose	Bit	Purpose		Bit	Purpose
0	NextState[0]	6	DrREG	12	LdIR	18	WrMEM		24	ChkCmp
1	NextState[1]	7	DrMEM	13	LdMAR	19	RegSelLo
2	NextState[2]	8	DrALU	14	LdA	20	RegSelHi
3	NextState[3]	9	DrPC	15	LdB	21	ALULo
4	NextState[4]	10	DrOFF	16	LdCmp	22	ALUHi
5	NextState[5]	11	LdPC	17	WrREG	23	OPTest

Table 4: Register Selection Map

RegSelHi	RegSelLo	Register
0	0	RX (IR[27:24])
0	1	RY (IR[23:20])
1	0	RZ (IR[3:0])
1	1	unused

Table 5: ALU Function Map

ALUHi	ALUlLo	Function
0	0	ADD
0	1	SUB
1	0	NAND
1	1	A + 1