VHDL Assignment #2: Design and Simulation of Digital Circuits

Description

2 Introduction

In this assignment, you will learn how to create a circuit using a schematic diagram in Quartus. You will then simulate the circuit in ModelSim. You will also learn how to use the test bench writer tool in Quartus. Finally, you will learn and practice the use of concurrent statements.

3 Learning Outcomes

After completing this assignment you should know how to:

• Create a schematic gate diagram of a logic circuit

• Use CAD tools and VHDL to implement logic functions

• Synthesize logic functions

• Perform functional simulation

In this assignment you will learn how to use the Altera Quartus II FPGA design and Modelsim software.

4 Creating a Schematic Diagram Design File

To get some practice with Quartus, you will design a simple 4-bit comparator circuit, which you should name firstname_lastname_comp. This circuit has two 4-bit inputs, A(0), A(1), A(2), A(3) and B(0), B(1), B(2), B(3), and a single 1-bit output, AeqB. The output is to be 1 when the two inputs have exactly the same values, and be 0 otherwise. The boolean equation for the output in terms of the inputs is derived as:

AeqB = (A(3) XNOR B(3)) AND (A(2) XNOR B(2)) AND (A(1) XNOR B(1)) AND (A(0) XNOR B(0)).

In the above, XNOR means the complement of the XOR operation.

In this course, you will learn two methods for describing circuits in Quartus:

• Gate-level schematic diagrams

• VHDL descriptions

Schematic diagrams are graphical descriptions of the circuit, while VHDL uses textual descriptions. For most of the designs in the course you will use VHDL, but schematic entry is a good practice to get started with Quartus. To describe a circuit via a schematic diagram, follow the steps below.

The first step is to open the project that was created in Assignment #1. Once you have opened the project, click on the “File” menu of the main Quartus window and select the “New” menu item. The dialog box shown below will appear.

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In the dialog box, select “Block Diagram/Schematic File” and click on “OK”. A new window will appear in the main area of the Quartus window. You will draw your circuit schematic in this new window.

A toolbar will also appear, containing shortcuts for commands relevant to drawing schematics.

Click on the toolbar item that is shaped like an AND gate. This will bring up the “symbol” window that will allow you to select which symbol to add to your schematic drawing. Note that the symbol window can also be opened by double-clicking anywhere within the schematic window. You will want to add an XNOR gate symbol to your schematic. This can be done in two ways. The first way is to expand the library directory to the primitives/logic directory and then scroll down to the XNOR item and select it.

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Select “FILE”>“New”>“Project” and, in the window that appears, give the project the name firstname_lastname_lab2.

Once you click OK, another dialog box will appear allowing you to add files to the project. Click on “Add Existing File” and select the VHDL file that was generated earlier (firstname_lastname_comp.vhd). You can also add files later.

The ModelSim window will now show your VHDL file in the Project pane.

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To simulate the design, ModelSim must analyze the VHDL files, a process known as compilation. The compiled files are stored in a library. By default, this is named “work”. You can see this library in the “library” pane of the ModelSim window.

The question marks in the Status column in the Project tab indicate that either the files have not been compiled into the project or the source file has changed since the last compilation. To compile the files, select Compile

• Compile All or right click in the Project window and select Compile > Compile All. If the compilation is successful, the question marks in the Status column will turn to check marks, and a success message will appear in the Transcript pane (see figure below).

The compiled VHDL files will now appear in the library “work”.

Since all of the inputs are undefined, if you ran the simulation now, the outputs would be undefined. So you need to have a means of setting the inputs to certain patterns, and of observing the outputs’ responses to these inputs. In ModelSim, this is done by using a special VHDL entity called a Testbench. A testbench is special VHDL code that generates different inputs that will be applied to your circuit so that you can automate the simulation of your circuit and see how its outputs respond to different inputs. Note that the testbench is only used in Modelsim for the purposes of simulating your circuit. You will eventually synthesize your circuits into a real hardware chip called an FPGA. However, you will NOT synthesize the testbench into real hardware. Because of its special purpose (and that it will not be synthesized), the testbench entity is unique in that it has NO inputs or outputs, and uses some special statements that are only used in test benches. These special statements are not used when describing circuits that you will later synthesize to a FPGA. The testbench contains a single component instantiation statement that inserts the module to be tested (in this case the firstname_lastname_comp module), as well as some statements that describe how the test inputs are generated.

After you gain more experience you will be able to write VHDL testbenches from scratch. However, Quartus has a

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At first, the “Wave” window will not have any signals in it. You can drag signals from the “Objects” window by click on a signal, holding down the mouse button, and dragging the signal over to the Wave window. Do this for all the signals. Now, to actually run the simulation, click on the “Run all” icon in the toolbar. If you get an incorrect output waveform, you will have to go back and look at your design. If you make a correction to your VHDL code, you will have to re-run the compilation of the changed files in ModelSim. Finally, to rerun the simulation, first click on the “Restart” button, then click on the “Run all” button.

The simulation you ran in the previous part of the lab just had a couple of input signal transitions, and did not test all possible input patterns. There are 2⁸ or 256 possible patterns in the gNN_comp circuit, so complete testing of the circuit will require you to simulate all of these patterns. In order to run through all possible 256 cases, we use a FOR LOOP that increments the value of code signal in the loop. This is done in the testbench shown below.

g e n e r a t e _ t e s t : PROCESS
BEGIN
FOR i	IN	0	t o	16	LOOP —	loop	over	all	A	values
A <=	s t d _ l o g i c _ v e c t o r ( t o _ u n s i g n e d ( i,4 ) ) ;								—	convert the loop variable i to s t d _ l o g i c _ v e c t o r
FOR j	IN	0	t o	16	LOOP —	loop	over	all	B	values

B <= s t d _ l o g i c _ v e c t o r ( t o _ u n s i g n e d ( j,4 ) ) ; —				convert	the	loop variable i to
s t d _ l o g i c _ v e c t o r
WAIT FOR 10	ns ;	—	suspend process for 10 n a n o s e c o n d s at the start of each loop
END LOOP; — end	the	j	loop
END LOOP; — end	the	i	loop
WAIT; — we have	gone		through all possible input	pa tt er n s,	so	suspend si m ul at or forever

END PROCESS g e n e r a t e _ t e s t ;

The process block generates all of the possible input patterns using a FOR loop. The RANGE attribute is equivalent to specifying the loop range as over the minimum value of the signal to its maximum value. Replace the “always” process block to perform the complete test. Note the convertor function of “to_unsigned” only works when its library (i.e., ieee.numeric_std.all) is called in the testbench.

Modify your testbench so that it performs the exhaustive testing. In the ModelSim program recompile the testbench and then restart and re-run the simulation. Look at the simulated cases and check to see if they are correct.

5 Concurrent Statements in VHDL

Combinational circuits can be described in VHDL using “Concurrent statements”. There are different types of concurrent statements in VHDL.

5.1 Direct Assignment

The simplest form of concurrent statements is the direct assignment. Below is an example of direct assignment which performs XOR operation between two variables:

c <= a XOR b ;

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5.2 Selected Signal Assignment or the “With/Select” Statement

Consider an n-to-1 multiplexer shown below. This block selects one of its n inputs and transfers the value of this input to the output terminal, i.e., output_signal.

The selected signal assignment allows to implement the functionality of a multiplexer:

w i t h c o n t r o l _ e x p r e s s i o n s e l e c t
o u t p u t _ s i g n a l <= value_1	when	o pt io n_ 1 ,
value_2	when	o pt io n_ 2 ,
…
value_n	when	option_n ;

Here, the value of the control_expression will be compared with the n possible options, i.e., option_1, option_2,

• . . , option_n. When a match is found, the value corresponding to that particular option will be assigned to the output signal, i.e., output_signal. For example, if control_expression is the same as option_2, then value_2 will be assigned to the output_signal. Note that the options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all possible values of the control_expression must be included in the set of options.

5.3 Conditional Signal Assignment or the “When/Else” Statement

The “when/else” statement is another way to describe concurrent signal assignments. In general, the syntax of the “when/else” statement is:

o u t p u t _ s i g n a l <= value_1	when	e x p r e s s i o n _ 1	e l s e
value_2	when	e x p r e s s i o n _ 2	e l s e
…
value_n ;

In this case, the expressions after “when” are evaluated successively until a true expression is found. The assignment corresponding to this true expression will be performed. If none of these expressions are true, the last assignment will be executed. We should emphasize that the expressions after the “when” clauses are evaluated successively. As a result, expressions evaluated earlier have higher priority as compared to later expressions. Considering this, we can obtain the conceptual diagram of this assignment as shown below. This figure illustrates a conditional signal assignment with three “when” clauses.

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5.4 Concurrent Statements at a Glance

Concurrent statements are executed at the same time and there is no significance to the order of these statements. This type of code is quite different from what we have learned in basic computer programming where the lines of code are executed one after the other.

The selected signal assignment or the “with/select” assignment allows us to implement the functionality of a mul-tiplexer.

The options of a “with/select” assignment must be mutually exclusive, i.e., one option cannot be used more than once. Moreover, all possible values of control_expression must be included in the set of options.

For the “when/else” statement, the expressions following the “when” clauses are evaluated successively. As a result, the expressions evaluated earlier have a higher priority as compared to the following expressions.

One important difference between the “with/select” and “when/else” assignment can be seen by comparing the conceptual implementation of these two statements. The “when/else” statement has a priority network; however, the “with/select” assignment avoids this chain structure and has a balanced structure.

6 VHDL Implementation of a 2-to-1 MUX

A multiplexer is a circuit that selects between several inputs and forwards it to a single output. In general, a 2ⁿ-to-1 MUX has 2ⁿ inputs with n selectors. A schematic diagram of a 2-to-1 multiplexer is given below.

According to the above schematic, the 2-to-1 multiplexer outputs the input signal A when the selector signal S is equal to 0 otherwise it outputs the input signal B. In this lab, you will implement this 2-to-1 multiplexer in VHDL using structural and behavioral styles. In the structural modeling of the 2-to-1 multiplexer in VHDL, the multiplexer is implemented using AND, OR or NOT gates only. More specifically, the structural description of the multiplexer literally realizes its boolean function. Describe the boolean function in VHDL using AND, OR or NOT gates only. Use the following entity declaration for your VHDL description of the 2-to-1 multiplexer:

l i b r a r y IEEE;

u s e IEEE.STD_LOGIC_1164.ALL;

u s e IEEE.NUMERIC_STD.ALL;

e n t i t y f i r s t n a m e _ l a s t n a m e _ M U X _ s t r u c t u r a l i s

P o r t ( A : i n s t d _ l o g i c ;

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	B	: i n		s t d _ l o g i c ;
	S	: i n		s t d _ l o g i c ;
	Y	:	o u t s t d _ l o g i c ) ;
	end f i r s t n a m e _ l a s t n a m e		_ M U X _ s t r u c t u r a l ;

Make sure to replace firstname_lastname with your full name. Once completed, you will describe the archi-tecture of the 2-to-1 multiplexer using behavioral style. In the behavioral description, you desrcribe the behavior of your target circuit and the synthesis tool creates a gate-level layout of your design. Use a single VHDL select assignment only and the entity declaration below to implement a behavioral description of the 2-to-1 multiplexer.

l i b r a r y IEEE;

u s e IEEE.STD_LOGIC_1164.ALL;

u s e IEEE.NUMERIC_STD.ALL;

e n t i t y f i r s t n a m e _ l a s t n a m e _ M U X _ b e h a v i o r a l i s

P o r t ( A : i n s t d _ l o g i c ;

• : i n s t d _ l o g i c ;

S : i n s t d _ l o g i c ;

• : o u t s t d _ l o g i c ) ;

end f i r s t n a m e _ l a s t n a m e _ M U X _ b e h a v i o r a l ;

Once described both behavioral and structural styles of the 2-to-1 multiplexer in VHDL, you are required to test your circuits. Write a testbench code and perform an exhaustive test for your VHDL descriptions of the 2-to-1 multiplexer.

• Questions

• 1. Explain your VHDL code.

• 2. Report the number of pins and logic modules used to fit your designs on the FPGA board. These results can be obtained from the flow summary tab in the table of contents menu in Quartus.

AeqB	2-to-1 MUX
Schematic	Structural Behavioral

Logic Utilization (in ALMs)

Total pins

3. Show a representative simulation plot for the introductory testing example. You can simply include a snapshot from the waveform that you obtained from ModelSim. In order to fully capture all the signals from the waveform, you can adjust the display range using the magnifier icons.

3. Show representative simulation plots for the exhaustive test.

3. Show representative simulation plots of the 2-to-1 MUX circuits for all the possible input values.

8 Deliverables

You are required to submit the following deliverables on MyCourses. Please note that a single submission is required per group (by one of the group members).

• Lab report. The report should include the following parts: (1) Names and McGill IDs of group members,

(2) an executive summary (short description of what you have done in this VHDL assignment), (3) answers to all questions in previous section (if applicable), (4) legible figures (screenshots) of schematics and simulation results, where all inputs, outputs, signals, and axes are marked and visible, (5) an explanation of the results obtained in the assignments (mark important points on the simulation plots), and (6) conclusions. Note – students are encouraged to take the reports seriously, points will be deducted for sloppy submissions.

• Project files. Create a single .zip file named vhdl#_firstname_lastname (replace # with the number of the current VHDL assignment and firstname_lastname with the name of the submitting group member). The

.zip file should include the working directory of the project.

McGill University ECSE 222 – Digital Logic (Fall 2022)