Description
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Phase 1: In-lab Exercises
1.1 Instructions
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You are expected to work in groups of 4 at each table. All brainstorming discussions must be done as a team to promote collaborative thinking.
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If you happen to be at a table with fewer than 4 people, you can choose to work with fewer people or let your TA’s know to assist you in nding extra partner(s).
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Download the collateral from Slack and use the skeletal les provided. Do not change the name of the les.
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Add your full name and UIN to the introductory comment present in each .hdl le.
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Complete the problem set provided in this document on your own sheet of paper. Make sure your drawings are clear and handwriting is legible. Show your work.
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Implement the .hdl, .tst, and .cmp le for each chip. Keep these handy because you will use them and turn them in for Project 2 Phase 2.
1.2 Submission
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Submissions must be done individually. Even though you are nding the solutions as a team, each of you is supposed to do the implementation individually, so we know you got the concepts.
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Including your name and UIN, turn in your sheet of paper with the solutions to the problem set by the end of the lab session. Include your name and UIN.
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In a zipped folder named LastName FirstName UIN Lab2.zip turn in the .hdl, .tst, and .cmp les before midnight on eCampus.
1
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(6 points) A Half Adder is characterized with two 1-bit data inputs a and b, a 1-bit data output sum, and a 1-bit carry output carry.
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(1=2 point) Draw the interface block diagram (inputs and outputs) of the Half Adder.
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Half Adder
(b) (1=2 point) Complete the truth table for the Half Adder.
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Inputs
Outputs
a
b
carry
sum
0
0
0
1
1
0
1
1
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(1 point) Write the logic expressions for outputs carry and sum from the truth table above, then minimize them using Boolean Algebra.
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(1 point) Draw logic gate diagrams to implement the minimized logic expressions for carry and sum.
(e) (3 points) Implement the .hdl, .tst, and .cmp les for the Half Adder chip.
Page 2
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(10 points) A Full Adder is characterized with two 1-bit data inputs a and b, a 1-bit carry input c, a 1-bit data output sum, and a 1-bit carry output carry.
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(1=2 point) Draw the interface block diagram (inputs and outputs) of the Full Adder.
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Full Adder
(b) (11=2 points) Complete the truth table for the Full Adder.
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Inputs
Outputs
a
b
c
carry
sum
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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(2 points) Write the logic expressions for outputs carry and sum from the truth table above, then minimize them using Boolean Algebra.
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(2 points) Draw logic gate diagrams to implement the minimized logic expressions for carry and sum.
(e) (4 points) Implement the .hdl, .tst, and .cmp les for the Full Adder chip.
Page 3
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(12 points) A 4-bit ripple carry adder Add4 is characterized by two 4-bit data inputs a[3 : 0] and b[3 : 0],
a 4-bit data output sum[3 : 0], and a 1-bit carry output carry.
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(4 points) Draw the inner logic block diagram of Add4 using one Half Adder and three Full Adders.
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a[3:0] b[3:0]
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4
4
4
carry sum
(b) (4 points) Draw the inner logic block diagram of Add4 using full adders only.
a[3:0] b[3:0]
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4
4
4
carry sum
(c) (4 points) Implement the .hdl, .tst, and .cmp les for the Add4 chip using full adders only.
Page 4