VHDL Assignment #3: Design and Simulation of Adder Circuits

Description

2 Learning Outcomes

After completing this lab you should know how to:

• Use VHDL statements to implement different adder circuits

• Write efficient VHDL codes

• Perform functional simulation

• Perform basic timing analysis

You will also have a better understanding of the concept of synthesis of logic circuits.

3 VHDL Description of Adder Circuits

In this assignment, you will be asked to perform the design and simulation of the following two adder circuits: (a) a 4-bit ripple-carry adder; and (b) a one-digit binary coded decimal (BCD) adder. Details of the assignments are described below.

3.1 Ripple-Carry Adder (RCA)

In this section, you will implement a structural description of a 4-bit ripple-carry adder using basic addition components: half-adders and full-adders.

3.1.1 Structural Description of a Half-Adder in VHDL

A half-adder is a circuit that takes two binary digits as inputs, and produces the result of the addition of the two bits in the form of a sum and carry signals. The carry signal represents an overflow into the next digit of a multi-digit addition. Using the following entity definition for your VHDL code, implement a structural description of the half-adder.

l i b r a r y IEEE;

u s e IEEE.STD_LOGIC_1164.ALL;

u s e IEEE.NUMERIC_STD.ALL;

e n t i t y h a l f _ a d d e r i s

p o r t ( a : i n s t d _ l o g i c ;

VHDL Assignment #3				2
	b : i n s t d _ l o g i c ;
	s :	o u t	s t d _ l o g i c ;
	c :	o u t	s t d _ l o g i c ) ;

end h a l f _ a d d e r ;

After you have described your structural style of the half-adder in VHDL, you are required to test your circuit.

Write a testbench code and perform an exhaustive test of your VHDL description of the half-adder.

3.1.2 Structural Description of a Full-Adder in VHDL

Unlike the half-adder, a full-adder adds binary digits while accounting for values carried in (from a previous stage addition). Write a structural VHDL description for the full-adder circuit using the half-adder circuit that you designed in the previous section. Use the following entity declaration for your structural VHDL description of the full-adder.

l i b r a r y IEEE;

u s e IEEE.STD_LOGIC_1164.ALL;

u s e IEEE.NUMERIC_STD.ALL;

e n t i t y f u l l _ a d d e r i s

p o r t ( a : i n s t d _ l o g i c ;

b : i n s t d _ l o g i c ;

c_in : i n s t d _ l o g i c ;

s : o u t s t d _ l o g i c ;

c_out : o u t s t d _ l o g i c ) ;

end f u l l _ a d d e r ;

After you have described your circuit in VHDL, write a testbench code and perform an exhaustive test of your VHDL description of the full-adder.

3.1.3 Structural Description of a 4-bit Ripple-Carry Adder (RCA) in VHDL

Using the half-adder and full-adder circuits implemented in the two previous sections, implement a 4-bit carry-ripple adder. Write a structural VHDL code for the 4-bit RCA using the following entity declaration.

	l i b r a r y IEEE;
	u s e IEEE.STD_LOGIC_1164.ALL;
	u s e IEEE.NUMERIC_STD.ALL;
	e n t i t y r c a _ s t r u c t u r a l i s
	p o r t	( A :	i n	s t d _ l o g i c _ v e c t o r	(3	downto	0) ;
		B :	i n	s t d _ l o g i c _ v e c t o r	(3	downto	0) ;
		S : o u t		s t d _ l o g i c _ v e c t o r	(4	downto	0));
	end	r c a _ s t r u c t u r a l ;

Note that S(4) contains the carry-out of the 4-bit adder. After you have described your circuit in VHDL, write a testbench code and perform an exhaustive test of your VHDL structural description of the 4-bit RCA.

3.1.4 Behavioral Description of a 4-bit RCA in VHDL

In this part, you are required to implement the 4-bit RCA using behavioral description. One way to obtain a behavioral description is to use arithmetic operators in VHDL (i.e., “+”). Write a behavioral VHDL code for the 4-bit RCA using the following entity declaration for your behavioral VHDL description.

l i b r a r y IEEE;
u s e IEEE.STD_LOGIC_1164.ALL;
u s e IEEE.NUMERIC_STD.ALL;
e n t i t y r c a _ b e h a v i o r a l i s
p o r t	( A :	i n	s t d _ l o g i c _ v e c t o r	(3	downto	0) ;
	B :	i n	s t d _ l o g i c _ v e c t o r	(3	downto	0) ;
	S : o u t		s t d _ l o g i c _ v e c t o r	(4	downto	0));
end	r c a _ b e h a v i o r a l ;

VHDL Assignment #3

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Make sure that your system settings look like this:

Click run (remember to set the simulator to Mentor Precision 2019.2 for this part), and you will be able to see the timing analysis information in the compiler log. In this example, the log looks like this:

For example, the critical path from input A(3) to output S(4) exhibits a positive slack of 15.019 ns, which means that the circuit meets the requirement.

VHDL Assignment #3

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4 Deliverables

Once completed, you are required to submit a report explaining your work in detail, including answers to the questions related to this lab. You will find the questions in the next section. You must also submit all of your VHDL, run.do, and .sdc files along with Log content of the synthesized circuits and timing analysis. You must also submit all of your testbench files. If you fail to submit any part of the required deliverables, you will incur grade penalties as described in the syllabus.

5 Questions

Please note that even if some of the waveforms may look the same, you still need to include them separately in the report.

1. Briefly explain your VHDL code implementation of all circuits.

2. Show representative simulation plots of the half-adder circuit for all possible input values.

3. Show representative simulation plots of the full-adder circuit for all possible input values.

4. Show representative simulation plots of both behavioral and structural descriptions of the 4-bit RCA for all possible input values.

5. Show representative simulation plots of both behavioral and structural descriptions of the one-digit BCD adder circuit for all possible input values.

6. Perform timing analysis of the one-digit BCD adder and find the critical path(s) of the circuit. What is the delay of the critical path(s)? Assuming that an additional delay of 10 ns can be added to the critical path(s) due to wiring, what should be the set_max_delay command to ensure a positive slack of 5 ns for the circuit (write the complete set_max_delay command).

7. Report the number of pins and logic modules used to fit your BCD adder designs on the FPGA board.

RCA	One-digit BCD adder
Structural Behavioral	Structural Behavioral

Logic Utilization (in LUTs)

Total pins

McGill University ECSE 222 – Digital Logic (Fall 2020)